Semiconductor devices, such as transistors, have reached well into the sub-micron range, e.g., below 0.25 microns. The semiconductor manufacturing industry has made continued advances in overall device speed and performance, while continually shrinking device size and increasing component density.
Transistors that comprise a bulk of these devices are manufactured using well-known processing methods. These processing methods are used to manufacture the very small gate dimensions that are now prevalent in the industry. In many designs these small gates are formed as complementary NMOS (n-channel) and PMOS (p-channel) transistors. One way in which these gates are manufactured is by first depositing a layer of polysilicon across a semiconductor wafer and then masking off either the NMOS or PMOS areas and doping the unmasked regions with the appropriate dopant. These doping steps are followed by a lithographic process that patterns the doped polysilicon layer into NMOS and PMOS gate electrodes, after which their respective source/drains are then ultimately formed.
Another way in which these gate structures are formed is by depositing a polysilicon layer across the semiconductor wafer and then using lithographic processes to pattern the layer into individual gate electrodes, which are then doped when the source/drain regions are doped, thus the gate electrodes receives essentially the same dosage as the source/drains.